愛普科技股份有限公司

擅長工具: SPICE, Verilog
其他條件: 
1.具DRAM 設計背景尤佳
2.熟悉類比電路設計流程
3.熟悉Verilog 語言佳
4.會使用Finesim, Hspice

1.類比電路設計
2 DRAM 電路設計與模擬
3.包含DRAM array, DRAM IO, DRAM power system 區塊

擅長工具: FPGA, Verilog

其他條件
1.熟悉Whole-chip integration流程
2.Understanding digital/analog design
3.Familiar with linux system and scripting language

1. High speed SerDes circuit design, like CTLE, CDR, DFE, PLL, DLL and TX Driver.
2. High efficient power management integrated circuit (PMIC) design, like LDO, DC-DC converter and envelop tracking (ET) power supply modulator.
3. High speed data converters, like SAR ADC, pipelined ADC, interleaved ADC, hybrid ADC, current steering DAC and switch-capacitor DAC's.
4. High speed DDR/LPDDR analog PHY circuit design and verification.
5. High resolution data converter, like noise shaping CT/DT DSM ADC/DAC and incremental ADC.
6. Ultra-low power analog/mixed-signal circuits design for IoT.
7. Analog circuit and chip integration of Serdes, PLL, Data Converter, PMU and PMIC.