擷發科技股份有限公司

1. Bachelor or Master Degree, major in Electrical Engineering, Electronic Engineering, Information Engineering or Computer Science.
2. Experienced in Verilog. Familiar with C/SystemVerilog/UVM is a plus.

1.Complete the front-end design tasks from RTL design to netlist

2.Main jobs contains spec study, architecture plan, RTL coding, simulation, debugging, Lint, CDC, synthesis, LEC, SDC, and STA

3.Support other functional teams (such as IP ,DFT , and P&R vendor) to deliver an SoC/ASIC design

4. Porting RTL Code to FPGA Platform

1. Bachelor or Master Degree, major in Electrical Engineering, Electronic Engineering, Information Engineering or Computer Science.
2. Experience with Verilog/System Verilog/UVM is preferred.
3. ARM Based SOC verification experience is a plus.

1. Develop and maintain block and chip level verification environment
2. Execute and manage test plan
3. In charge of Subsystem DV for SPEC-IN Project