求才職稱 | 資格條件 | 工作內容 | 待遇 | 工作地點 | 需求人數 |
SoC Designer
(理工科系職缺:是)
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工作經驗 : 不拘 學歷要求 :大學以上 科系要求 :電機電子工程相關,資訊工程相關,其他工程相關 擅長工具 Perl Python TCL ARM ASIC Circuit Design EDA FPGA RTL Synopsys Verilog 工作技能 撰寫硬體語言程式 開發電子電路系統 電子電路設計 基礎數位電路 數位晶片產品開發 數位電路分析設計 數位電路驗證
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1. SoC top/sub-system architecture planning and design integration. 2. SoC design implementation from logic synthesis to physical implementation. 3. Work with multiple teams and drive RTL to GDS flow. [Requirement] 1.Familiar with Verilog HDL and digital IC design flow, including RTL sign-off, Synthesis, LEC, STA, timing-signoff. 2.Better to have DFT/ATPG and MBIST knowledge. 3.Better to have FPGA implementation experience.
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面議
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新竹市
新竹市東區光復路二段101號清大北校區育成中心(2025將進駐新竹科學園區X基地第一軟體大樓)
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Design Verification
(理工科系職缺:是)
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工作經驗 : 不拘 學歷要求 :大學以上 科系要求 : 電機電子工程相關,其他工程相關 擅長工具 EDA RTL Verilog 工作技能 撰寫硬體語言程式 數位晶片產品開發 數位電路分析設計 數位電路驗證
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1. Design verification with SystemVerilog/UVM, C/C++ 2. Integration test environment with VIP 3. Develop checker and scoreboard. 4. Verify design with SystemVerilog assertion. 5. Test plan for a verification task. [Requirement] 1. Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming. 2. Better to have SoC design and bus concept.
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面議
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新竹市
新竹市東區光復路二段101號清大北校區育成中心(2025將進駐新竹科學園區X基地第一軟體大樓)
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Digital IC Designer
(理工科系職缺:是)
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工作經驗 : 不拘 學歷要求 :大學以上 科系要求 :電機電子工程相關,其他工程相關
擅長工具 TCL ASIC EDA FPGA RTL Synopsys Verilog VHDL 工作技能 撰寫硬體語言程式 數位晶片產品開發 數位電路分析設計 數位電路驗證
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[job description] Wolley is seeking candidates for a digital design engineer position. You will join an experienced team designing next-generation memory, storage controllers, and high-speed interface standard. You will also contribute to design concept discussion, architecture definition, as well as design implementation. ‧ Architecture design and RTL implementation ‧ System bus and related peripheral designs ‧ SoC and emulation platform design ‧ SoC system performance analysis [Requirement] 1. Bachelor's or Master's degree in Electrical Engineering or related fields 2. Familiar with RTL design, SystemVerilog, front-end design flow 3. The following working knowledge is desired: * Python programming * TCL scripting * Universal Verification Methodology (UVM) * Low power design and analysis
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面議
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新竹市
新竹市東區光復路二段101號清大北校區育成中心(2025將進駐新竹科學園區X基地第一軟體大樓)
| 5 |
System Software Engineer
(理工科系職缺:是)
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工作經驗 : 不拘 學歷要求 : 大學以上
擅長工具 Linux C C++ Drivers 工作技能 軟體工程系統開發 軟體程式設計
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We are seeking a skilled System Software Engineer to join our engineering team, specializing in Linux kernel and driver development. The successful candidate will have a robust understanding of storage-related subsystems and expertise in PCIe, which is a plus. This role involves developing system-level software that enables Wolley CXL product, and enhance its performance and reliability.
Key responsibilities: ‧Design and develop system software, focusing primarily on Linux kernel modules and drivers. ‧Proficient in programming languages such as C and C++ ‧Familiar with storage-related subsystems. ‧Collaborate with hardware engineers to design and develop integrated solutions. ‧Participate in code reviews and maintain high standards for code quality and efficiency Good to have: ‧Familiar with SPDK ‧Familiar with NVMe
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面議
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新竹市
新竹市東區光復路二段101號清大北校區育成中心(2025將進駐新竹科學園區X基地第一軟體大樓)
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