求才職稱 | 資格條件 | 工作內容 | 待遇 | 工作地點 | 需求人數 |
[Y25 TW HSZ Internship] Signal and Power Integrity Engineer for Advanced Packaging Solutions - Intern
(理工科系職缺:是)
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· Major in Electrical Engineering /Electrical and Communication · Knowledge: Electromagnetic theory, Microwave circuit, Signal integrity · Familiar with ANSYS HFSS is preferred · Familiar with use of VNA is preferred · With an effective in-school student status
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1. Electrical measurement with use of VNA and 2. Electrical simulation with EDA tools
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月薪:30000 - 50000
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新竹市
Hsinchu Office - 新竹市東區中華路二段190號7F (Ambassador Hotel building)
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[Y25 TW HSZ Internship] Advanced Packaging Development Project Support
(理工科系職缺:是)
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· Major in Material Science & Engineering/Physics/Mechanical Engineering · Knowledge: physical (electrical, mechanical, thermal) & chemical material properties / statistical theory · Familiar with JMP DOE is preferred · Familiar with SmartSheet or MS Project software is preferred · Familiar with failure analysis (X-ray, Optical microscope, SEM, EDX, AES, ESCA) is preferred · With an effective in-school student status
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1. Advanced packaging enablement project management support
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月薪:30000 - 50000
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新竹市
Hsinchu Office - 新竹市東區中華路二段190號7F (Ambassador Hotel building)
| 2 |
[Y25 TW HSZ Internship] FOUNDRY MFG EFFICIENCY Engineer - Intern
(理工科系職缺:是)
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· Major in Computer Science / Electrical Engineering · Knowledge: Algorithms, Data Structures , Machine Learning · Familiar with Python/C++ is preferred · With an effective in-school student status
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1. Assist of tool development, data handling and machine learning development to improve production data analysis efficiency
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月薪:30000 - 50000
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新竹市
Hsinchu Office - 新竹市東區中華路二段190號7F (Ambassador Hotel building)
| 1 |
[Y25 TW HSZ Internship] Yield Management and System Engineer - Intern
(理工科系職缺:是)
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· Major in Computer Science / Electrical Engineering · Knowledge: Algorithms, Data Structures , Machine Learning/AI , Semiconductor industry exposure · Familiar with Python/C++/JMP/Shell Scripting · Good at English communication in written and verbal · Team player and willing to learn · With an effective in-school student status
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1. Assist of system and tool development for data engineering and data scientist projects 2. Ad-hoc help on small projects to contribute to yield learnings 3. Work with data scientist to explore new ideas and implement in production flow
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月薪:30000 - 50000
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新竹市
Hsinchu Office - 新竹市東區中華路二段190號7F (Ambassador Hotel building)
| 1 |
[Y25 TW TPE Internship] Field Application Engineer - Intern
(理工科系職缺:不拘)
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· Major in Business Management, Economics, Engineering, Computer Science or similar. · Good at English verbal and written communications · Good in MS Office knowledge, Excel, PowerPoint · Good analytical and data management skills · Familiar with PC product would be a plus · Available to work at least 3 working days a week · With an effective in-school student status
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This is one year internship program and main responsibilities will include: 1. Sales operation, business data analysis and marketing data research 2. Technical pre-sales activities includes design win tracking, sample support and develop/generate KPI dashboard"
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月薪:30000 - 50000
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臺北市
Taipei Nangang Office - 台北市南港區忠孝東路7段369號20樓
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[Y25 TW TPE Internship] Platform Debug Engineer - Intern
(理工科系職缺:是)
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Minimum Qualifications: · Software Engineering background, familiar with programming languages - C/C++, python · IA based PC knowledge · With an effective in-school student status Preferred Qualifications: · Computer Science / Electrical Engineering · Familiar with AI and its applications
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1. Responsibilities may be quite diverse of a software technical nature. 2. Experience and education requirements will vary significantly depending on the unique needs of the job. 3. This position will sit in the Platform Debug Team, and be responsible for silicon and platform debug tools development and maintenance. It also involves turning new/creative ideas into practical products.
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月薪:30000 - 50000
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臺北市
Taipei Nangang Office - 台北市南港區忠孝東路7段369號20樓
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[Y25 TW TPE Internship] Platform SW Engineer - Intern
(理工科系職缺:是)
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Minimum Qualifications: · Software Engineering background, familiar with programming languages - C/C++, python · Solid knowledge on the Machine learning, Deep learning and Generative AI. Understand how to implement the integration from the model in HF. · IA based PC knowledge · Be familiar with the GenAI framework in Open Vino · Have passion to develop AI usage on PC and Edge devices. · With an effective in-school student status Preferred Qualifications:
· Majoir in Computer Science / Electrical Engineering · Familiar with AI and its applications
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1. Responsibilities may be quite diverse of a software technical nature. 2. Experience and education requirements will vary significantly depending on the unique needs of the job. 3. This position will sit into Platform software team, be responsible for developing and enabling features to support AI PC segment. It also involves with implementing the Proof of Concept to demo new ideas on AI PC .
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月薪:30000 - 50000
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臺北市
Taipei Nangang Office - 台北市南港區忠孝東路7段369號20樓
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[Y25 TW TPE Internship] AI Software Solutions Engineer - Intern
(理工科系職缺:是)
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Minimum Qualifications: · Background in Software Engineering, familiar with programming languages such as C/C++ and Python. · Knowledge of Machine Learning, Deep Learning, and Generative AI. · Knowledge of IA-based PC architecture. · Familiarity with the GenAI framework in OpenVINO. · Passion for developing AI applications · With an effective in-school student status Preferred Qualifications: · Familiarity with AI models and its applications · Experience with AI benchmarking and performance optimization. · Strong problem-solving skills and ability to work collaboratively in a team environment. · Excellent communication skills to effectively convey technical concepts.
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1. Collaborate with internal teams and external partners to deliver optimized AI solutions for NAS products using Intel technologies. 2. Research technical trends and prototype AI software, including open-source libraries and models. 3. Optimize AI model performance through expertise in AI frameworks, algorithms, and hardware. 4. Develop and adjust AI models to enhance performance and address issues. 5. Work with AI algorithm and framework engineers to optimize end-to-end AI models for Intel hardware. 6. Serve as a technical advisor and enablement partner. 7. Collaborate with Intel product development teams to accelerate and optimize AI solutions. 8. Deliver competitive benchmark collateral and drive key workloads into product requirements.
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月薪:30000 - 50000
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臺北市
Taipei Nangang Office - 台北市南港區忠孝東路7段369號20樓
| 1 |
[Y25 TW TPE Internship] Platform FW and AI Application Engineer - Intern
(理工科系職缺:是)
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· Knowledge: Machine learning, AI application, LLM, DevOps automation, · Familiar with Python/C/llma2/hugging face is preferred · With an effective in-school student status
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1. Designs, builds, and integrates applications and platforms to support Intel's business needs. 2. Responsibility includes developing application, validation, data analysis, debug and deployment tools to improve operation efficiency.
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月薪:30000 - 50000
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臺北市
Taipei Nangang Office - 台北市南港區忠孝東路7段369號20樓
| 1 |
[Y25 TW TPE Internship] System Engineer - Intern
(理工科系職缺:是)
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Min. Qualifications: · Major in Computer Science / Electrical Engineering · Software Engineering capability, familiar with programming languages - C/C++, python · IA based PC knowledge · With an effective in-school student status Preferred Qualifications: · Familiar with AI and its applications
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1. Exploration of the System Integration of UX and KEI on AIPC & Smart Base which can bring more value for OxMs from a System perspective. 2. Cultivation of the young generation/going to graduate students.
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月薪:30000 - 50000
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臺北市
Taipei Nangang Office - 台北市南港區忠孝東路7段369號20樓
| 1 |
[Y25 TW HSZ Summer Internship] JR0270139 Applications Support Engineer - Intern
(理工科系職缺:是)
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Minimum Qualifications: · Candidate must possess a BS/MS student on Electrical/Computer Engineering, Computer Science, or related STEM fields. · Must be able to commit to at least a 2-month internship from July 2025 to August 2025. · With an effective in-school student status Preferred Qualifications: · Self-motivated mindset. Good communication skill, verbal and written. · Programming skill such as Python, Perl, C++, or SKILL language. · IC design schoolwork, research, project experience.
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月薪:30000 - 50000
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新竹市
Hsinchu Office - 新竹市東區中華路二段190號7F (Ambassador Hotel building)
| 1 |
[Y25 TW HSZ Summer Internship] JR0270136 PDK Support Intern (Physical Design)
(理工科系職缺:是)
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Minimum Qualifications: · Major in Electrical/Computer Engineering. VLSI related courses and projects preferred. · Knowledge on physical design implementation flow. · Familiarity in scripting languages such as TCL, Python, and Perl. · Self-Motivated with good communication skills and strong problem-solving skills. · With an effective in-school student status Preferred Qualifications: · Experience with industry EDA APR tools such as Fusion Compiler or Innovus. · Intel and/or external foundry process technology knowledge in advance nodes. · Master's degree is a plus.
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· At Intel, Design Enablement (DE) is one of the key departments enabling Intel to deliver winning products in the marketplace. · You will have a chance to work with experienced teammates on cutting-edge technologies. · This DEAS (Design Enablement Application Support) role is to support Intel leading edge PDKs (Process-Design-Kits) on digital/ASIC related areas. · You will review User Guide, Training Documents, and help in regression automation and/or user support.
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月薪:30000 - 50000
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新竹市
Hsinchu Office - 新竹市東區中華路二段190號7F (Ambassador Hotel building)
| 1 |
[Y25 TW HSZ College Graduate] JR0269427 PDK Support Engineer (Physical Design)
(理工科系職缺:是)
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Minimum Qualifications: · Major in Electrical/Computer Engineering. VLSI related courses and projects preferred. · Knowledge on physical design implementation flow. · Familiarity in scripting languages such as TCL, Python, and Perl. · Good communication skills and strong problem-solving skills. Preferred Qualifications: · Experience with industry EDA APR tools such as Fusion Compiler or Innovus. · Intel and/or external foundry process technology knowledge in advance nodes. · Master's degree is a plus.
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Job Description · At Intel, Design Enablement (DE) is one of the key departments enabling Intel to deliver winning products in the marketplace
· You will directly drive and work with DE cross functional teams to ensure design-kit leadership for customer enablement of cutting-edge technologies. · This DEAS (Design Enablement Application Support) role is to support Intel leading edge PDKs (Process-Design-Kits) on digital/ASIC related areas. · You will directly interact with internal or external customers to outline outstanding requirements, root causing PDK issues, then collaborate with DE PDK team to come out with solution or PDK intercept plan. · You will own and maintain training documents, user guide, and act as reviewer for various PDK documents.
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面議
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新竹市
Hsinchu Office - 新竹市東區中華路二段190號7F (Ambassador Hotel building)
| 1 |
[Y25 TW HSZ College Graduate] JR0270134 Design Rule Development and QA Engineer
(理工科系職缺:是)
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Minimum Qualifications: · Candidate must possess a MS degree or above in Electrical/Computer Engineering or related field. Experience in the following: · Solid knowledge/experience of process and/or OPC and/or mask in advanced nodes. · Strong knowledge of design layout structure and/or std. cell development. · Experienced in working with design rule definitions. · Experienced in quality assurance for design rule and/or design rule check. · Industry standard CAD tools/flows for digital and/or analog design. · Software development/programming in high-level languages (e.g. Python, C/C++, TCL, Perl). · Experienced in implementation of high-level language compiler/interpreter.
* **Limiting of wordings. Please refer to the job link to access in full
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About the role · You must fully understand the design rule intent from discussion and documents. · To ensure rule quality you are responsible for test and capture the corner cases. · There are approaches like pattern testing, script for sanity check, etc. · You must have good communication skills to interact with cross teams. · Apply your analytic methods to identify and solve the problems. · We are looking for several design rule development and QA engineers that can fully develop, test, and release design rule QA collaterals. · Support design rule formation and development. · Align and standardize rule specification. · Create and maintain test pattern by EDA tools you are familiar with. · Develop and support complex algorithms for creating and manipulating layout design data. * **Limiting of wordings. Please refer to the job link to access in full
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面議
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新竹市
Hsinchu Office - 新竹市東區中華路二段190號7F (Ambassador Hotel building)
| 1 |
[Y25 TW HSZ College Graduate] JR0270135 Design Rule Verification Engineer
(理工科系職缺:是)
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Minimum Qualifications · Candidate must possess a BS degree with 1+ years of experience or an MS degree in Computer Science, Computer Engineering, Electrical Engineering, or related discipline. · Software programming skills in Python, Perl or, TCL. · Effective communication skills, willing to discuss with teams. Preferred Qualifications · 3+ months of semiconductor industry experience. · 3+ months experience with Unix/Linux operating system. · Proven ability of issue analysis, problem solving, and bring closure. · Industry standard CAD tools/flows for digital and/or analog design. · CAD tool scripting languages. (e.g. Calibre DESIGNrev, Cadence SKILL) · Minimum of 1 year of experience in DRC runset development using any of the following EDA tools: -Siemens Calibre -Synopsys ICV -Cadence Pegasus * **Limiting of wordings. Please refer to the job link to access in full
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Major Duties and Responsibilities Include: · Thoroughly understand the design rule intent through discussions and documentations. · Candidate should have effective verbal or written communication and analytical problem solving and troubleshooting skills in design rule development. · You will utilize modern design rule development methodologies, programming languages, domain knowledge, test, and release design rule QA collaterals. * * * **Limiting of wordings. Please refer to the job link to access in full
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面議
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新竹市
Hsinchu Office - 新竹市東區中華路二段190號7F (Ambassador Hotel building)
| 2 |