公司人數:500
資本額:1800000
地址:新竹市東區關新路27號5F-5

洽詢電話: | HR

線上登錄履歷

SiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors.

營業項目

Cloud service
-Core Designer for RISC-V Cores
-Chip Designer for RISC-V based SoC
Products
-Boards and Software
-RISC-V Open Source and ecosystem construction

應徵須知

薪資福利

零食櫃/咖啡吧/員工進修補助/醫療補助/交通津貼補助/旅遊補助/健身費用補助/部門聚餐



目前共有 12 個職缺類型

求才職稱資格條件工作內容待遇工作地點需求人數
System Modeling Engineer

(理工科系職缺:)

Essential Skills:
- Knowledge of architecture and micro-architecture concepts such as pipelines, caching, coherence, interconnects and ddr controllers
- Excellent C++ knowledge (including some C++11 experience)
- Excellent Python knowledge
- Excellent debugging & problem solving skills
- Excellent software engineering skills including knowledge about data structure and algorithms
- Some simulation experience

Desirable Skills:
- Experience with computer architecture simulators
- SystemC/TLM2.0
- RISCV Architecture knowledge
- Shell programming
- Knowledge of distributed version control systems (git)
- Experience interacting with open source projects


The system modeling engineer will maintain simulation infrastructure as needed to enable the Architecture's wider mission.
This includes:
- Maintaining existing gem5 and other simulation infrastructure.
- Implementing and maintaining models of SiFive CPU and System IP. For example, implementing a SiFive high-end CPU pipeline stage timing model, a new interrupt controller model or a new accelerator model.
- Based on the candidate's experience, the role can offer significant freedom to enhance and extend the simulation infrastructure and drive improvements in tools that are heavily relied-upon by the Software group.
- Interacting with the external gem5 open source community.
面議 新竹市
新竹市關新路27號5樓之5
2
Verification Engineer

(理工科系職缺:)

- A conscientious and thorough approach to Design Verification
- Attention to detail. Thoroughness is essential in this role.
- Solid understanding of processor and SoC architecture, or a strong desire and ability to learn same
- A thorough understanding of the high-level verification flow methodology (testplan generation, test generation, failure analysis, code coverage, iteration until coverage closure).
- Ability to effectively assess the current state of a design’s verification posture, remaining state space to be covered, and efficient methods to achieve verification closure
- Ability to learn languages and methodologies that are not part of the industry standard approach to verification (Scala, Chisel, etc.)
- Master’s degree required with emphasis in Electrical Engineering, Computer architecture, or Computer Science


RISC-V is a groundbreaking CPU instruction set and architecture. Along with being an open-source instruction set, RISC-V is informed by decades of industry experience with various RISC processor designs, while being unencumbered with the necessity of backward compatibility. It is a unique opportunity to base a processor design on sound engineering principles, and the successful applicant will have comprehensive daily hands-on exposure to this architecture. While several companies are pursuing RISC-V design, only SiFive is founded and actively managed by the inventors of RISC-V. This is not an academic exercise; we have real customers and real silicon.

As a Verification Engineer on the Design Verification team, you will participate in the definition, implementation, and execution of our verification strategy, as well as being a key participant in the analysis of our verification quality of results.
This verification position is a highly visible role, the simple purpose of which is to ensure the silicon works. What will you work on when you join our team? By its design philosophy, RISC-V is highly configurable, and we have several different configurations in our design pipeline, with various combinations of supported instruction set and with various peripherals and bus interconnect architectures. Implementing design verification methodologies that can accommodate such variation is a challenging task, to be addressed in this role.

you will responsible for:
-Architect test methodologies applicable to a wide range of processor and SoC designs
-Perform initial debug of test failures to identify design errors
-Collaborate closely with the design team to address any design errors
-Understand custom microprocessor and SoC designs from an architectural level, and use this understanding to envision effective verification strategies for these designs
-Create a test plan to codify this strategy, taking account of such issues as design feature priority, potential customer impact, coverage -metrics generation and measurability, etc.
-Create test suites (UVM, C, or otherwise, as needed) to execute this strategy
-Drive the execution of these test suites (scripting, Makefiles, etc.)
-Analysis of test results, including RTL or higher-level debug of test failures
-Interact with the design team to help drive bug closure
面議 新竹市
新竹市關新路27號5樓之5
2
GPU Software Engineer

(理工科系職缺:)

Required Qualifications
-Solid experience with one or more industry standard graphics APIs: OpenGL/OpenGLES/OpenCL
-Solid experience with GPU and CPU performance optimization techniques
-Experience in Linux GPU driver porting and integration with Linux based GUI systems
-A bare minimum of 4 to 10 years of recent experience in GPU driver integration, debugging and performance tuning

Desirable Qualifications
- Experience with Linux X-windows system and “DRM/DRI/Mesa”
- Experience in GPU architecture and performance tuning/evaluation is a plus


You will be responsible for:
GPU performance tuning and optimization, OpenGL/OpenGLES, Linux X-window driver (DRI/DRM/MESA), Linux GPU driver and open source software development/integration.
面議 新竹市
新竹市關新路27號5樓之5
2
Benchmarking & Performance Engineer

(理工科系職缺:)

Required Qualifications:
- Experienced with processor micro-architecture
- Experienced with micro-architecture performance analysis
- Experienced with representative workload extraction, e.g., SimPoint
- MS in Computer Science or Electrical Engineering required



Desirable Qualifications
- Experienced with simulator/model design
- Experienced with data science
- Experienced with web development


You will be responsible for:
- Root cause the the performance difference caused by either SW and/or HW.
- Create representative workload
- Design micro-benchmark for competitor micro-architecture analysis
- Design workload analyzer to extract workload characteristics
- Create insightful analysis report by data science
- Visualize micro-architecture activities to aid performance analysis
面議 新竹市
新竹市關新路27號5樓之5
2
Computer Vision Software Engineer

(理工科系職缺:)

Required Qualifications
- Experience with DSP and Vector architecture
- Experience with OpenCV/OpenVX is a must
- Experienced in developing software for computer vision, machine learning, image processing or computer graphics applications
A bare minimum of 4 to 10 years of recent experience in performance tuning and optimization in Computer Vision

Desirable Qualifications
- Experienced with vision application middleware integration like Camera, Surveillance or DVR is plus
- Experienced with ISP and Camera driver is plus
- Experienced with Caffe/Tensorflow/Glow is plus


The range of software that you will be responsible for will include Computer vision application/library optimization, DSP programming, OpeCV/OpenVX/OpenCL, Linux BSP, RTOS, and open source software development/integration. 面議 新竹市
新竹市關新路27號5樓之5
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AI Engineer

(理工科系職缺:)

Required Qualifications:
-A bare minimum of 2 to 7 years of recent hands-on experience building applications for AR, VR, Drones, IoT, or AI
- Experience in training models using deep learning frameworks: Caffe/Tensorflow/Tensorflow-Lite
- Experience with neural network model porting

Desirable Qualifications
- Experience in neural network algorithm development;
- Experience in retraining models maintaining accuracy;
- Experience with DSP programming;
- Experience in system performance tuning;
- Experience in Linux driver development;
- Experience with Glow/TVM/NVM/TensorRT/Tensorflow compiler portion.


The range of software that you will be responsible for and involved with includes: deep learning applications/middleware integration, quantization, retaining development, compute library optimization, NN model porting, performance tuning, system level performance debugging, and open source software development/integration. 面議 新竹市
新竹市關新路27號5樓之5
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Software Engineer for Vector library (Audio and AI)

(理工科系職缺:)

Required Qualifications
- Experienced with training model using deep learning frameworks: Caffe/Tensorflow/Tensorflow-Lite
- Experienced with neural network model porting
- Experienced with Glow/TVM/NVM/TensorRT/Tensorflow compiler portion is plus
- Hands-on experience building applications for AR, VR, Drones, IoT, or AI

Desirable Qualifications
- Experienced with neural network algorithm development is plus
- Experienced with retraining model maintaining accuracy
- Experienced with DSP programming is plus
- Experienced with system performance tuning is plus
- Experienced with Linux driver development is plus


The range of software that you will be responsible for will include Deep learning application/middleware integration, quantization and retrain development, Compute library optimization, NN model porting, performance tuning, system level performance debugging, and open source software development/integration. 面議 新竹市
新竹市關新路27號5樓之5
2
DevOps Software Engineer

(理工科系職缺:)

Required Qualifications:
- Build and maintain CI pipelines using build and release orchestration tools (GitLab, Docker, Kubernetes, Jenkins, Travis CI, etc)
- Familiarity of DejaGnu test framework and Expect scripting language
- Familiarity of version control tool GIT
- Experience in scripting (BASH, Perl, Powershell, Python) and building required automation

Desirable Qualifications
- Strong system administration (Linux/Unix or Windows) at the command-line level is a plus
- Experience with GitHub & Open Source is a plus


As a DevOps Software Engineer within software R&D team, you will play a key role in building a CI/CD platform initiative to automate and increase to delivery of our work across most software projects. To be successful you will need to have the ability to quickly understand various aspects of the software projects and how that translates into robust and scalable continuous delivery pipelines. You will need to use your deep experience in delivering features using Agile methodologies, specifically Scrum, for this role. In addition, you’ll use your passion for analytics to measure pipeline effectiveness and optimize where needed. 面議 新竹市
新竹市關新路27號5樓之5
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Compiler Software Engineer

(理工科系職缺:)

Required Qualifications:
- Good understanding of compiler and toolchain technology
- Familiarity of LLVM or GNU toolchain
- Familiarity of version control tool GIT
- Experienced with LLVM/GCC/other toolchain development
- Knowledge in RISC ISA and its optimization

Desirable Qualifications:
- Experienced with Auto Vectorization optimization is a big plus
- Familiarity with Vector/SIMD application development is a plus
- Familiarity of build system, like autotool or cmake is a plus


This job will participate in developing compiler and related toolchain for RISC-V processors. We are looking for talents who are familiar with RISC-V processor architecture, strong knowledge on compiler optimization, experienced in performance analysis. You will be involved in analyzing benchmarks and real world applications, and research for opportunities to improve them from compiler and tools' perspective. 面議 新竹市
新竹市關新路27號5樓之5
2
Toolchain Software Engineer

(理工科系職缺:)

Required Qualifications:
- Good understanding of compiler and toolchain technology
- Familiarity of LLVM or GNU toolchain
- Familiarity of version control tool GIT
- Experienced with LLVM/GCC/other toolchain development
- Knowledge in RISC ISA and its optimization

Desirable Qualifications
- Experienced with Linker Relaxation or Link Time Optimization is a big plus
- Familiarity with Vector/SIMD application development is a plus
- Familiarity of build system, like autotool or cmake is a plus


This job will participate in developing compiler and related toolchain for RISC-V processors. We are looking for talents who are familiar with RISC-V processor architecture, strong knowledge on compiler optimization, experienced in performance analysis. You will be involved in analyzing benchmarks and real world applications, and research for opportunities to improve them from compiler and tools' perspective. 面議 新竹市
新竹市關新路27號5樓之5
2
Debugger Software Engineer

(理工科系職缺:)

Required Qualifications:
- Good understanding of toolchain and debugger technology
- Familiarity of LLVM or GNU toolchain
- Familiarity of version control tool GIT
- Familiarity of ELF binary format
- Experienced with GDB or LLDB debugger development
- Knowledge in RISC ISA and its optimization

Desirable Qualifications
- Experienced with profiling tool is a plus
- Experienced with ICE/JTAG/OpenOCD is a big plus
- Familiarity of build system, like autotool or cmake is a plus


This job will participate in developing debugger and related toolchain for RISC-V processors. We are looking for talents who are familiar with RISC-V processor architecture, strong knowledge on embedded software debugging, experienced in debugger, binary utilities, and ELF binary format. You will be involved in debugging and analyzing benchmarks and real world applications with any debugging and profiling tools. 面議 新竹市
新竹市關新路27號5樓之5
2
CPU Design Engineer

(理工科系職缺:)

Required Qualifications:
- Knowledge of CPU architecture;
- Proficiency with hardware (RTL) design in Verilog, System Verilog, or VDHL;
- Attention to detail and a focus on high-quality design;
- Ability to work well with others and a belief that engineering is a team sport;
- Knowledge of at least one object-oriented and/or functional programming language;
- BS/MS in EE, CE, CS or a related technical discipline, or equivalent experience.

Desirable Qualifications:
Experience with Scala and/or Chisel;
Knowledge of RISC-V architecture;
Experience with Git/Github, Jira, Confluence;
Background of successful CPU development from architecture through tapeout.


SiFive is looking for hardware engineers who are passionate about designing industry leading CPUs to help drive the tidal wave of adoption of RISC-V as the architecture of choice for SOC designs across a broad variety of vertical applications. We’re creating massively customizable IP and improving time-to-market by designing hardware as highly configurable generators. We're leveraging technology and ideas from the software industry to execute hardware design with the agility of software development.
We build and maintain multiple CPU lines using the Chisel hardware construction library embedded in the Scala language, and are seeking motivated individuals to enhance our existing CPU lines as well as develop new ones.
Join us, and surf the RISC-V wave with SiFive!

Designing the best CPU cores in the world, based on the revolutionary open RISC-V architecture
Mastering the art of designing hardware as configurable generators in a hardware-enhanced software language
Working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance

Responsibilities:
- Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU Core generators in Chisel
- Design in extensive configurability as a first-class consideration
- “Plumb” new design content into the SiFive’s Chisel/FIRRTL framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software
- Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans;
- Ensure that knowledge is shared via great documentation and a participation in a culture of collaborative design.
面議 新竹市
關新路27號5樓之5
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