求才職稱 | 資格條件 | 工作內容 | 待遇 | 工作地點 | 需求人數 |
數位晶片設計工程師(前端) / Digital IC Design Engineer (Frontend)
(理工科系職缺:是)
|
## Skill: - Familiar with Verilog RTL implementation from a matlab, python or c algiorithm. - Familiar with RTL simulation, timing analysis. - Familiar with FGPA digital validation and test pattern generation using (system)ILA, logic analyzer, high-speed oscilloscope, etc. - Familiar with Xilinx FPGA serdes IO, and selectIO. - Familiar with Xilinx IP design and packaging. - Familiar with at least one FPGA device. - Familiar with Custom IP and SoC integration is a plus.
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## Job Description: The candidate will work closely with DSP algorithm team and software team to propose functional architecture and implement DSP algorithm using RTL and verified on a Xilinx FPGA. The verified design will either be passed to back-end for P&R or as a FPGA device product for early customer demo. The candidate will work with massive I/O throughputs using a parallel of high speed serdes.
| 月薪 70,000元 ~ 140,000元 |
新竹市
新竹市東區公道五路三段1號7樓之8
| 3 |
數位信號處理工程師 / DSP Engineer
(理工科系職缺:是)
|
-(Optional) 應徵者若有熟悉下列信號處理之相關知識或技術之一項或多項者,敬請在求職履歷中特別註明並附相關經歷(曾參與的專題計畫或修習過的課程、或其他工作經驗等),將以更加優沃的待遇優先考慮:(強調此項者可以完全不熟悉FPGA實作)
- 矩陣分解(SVD, EVD, QR,等) - 信號時頻分析及原理、 - 波束形成、 - 載波頻率偏移(CFO)之校正補償、 - Optimal receiver(例如MMSE接收器) - compressive sensing演算法設計及原理 - 傳輸波形最佳化 - 子空間演算法(MUSIC, ESPRIT, 等)
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1. Digital signal processing for wireless radar signals. 2. Performance evaluation of algorithm design. 3. (Optional) Some basic understanding of FPGA/RTL is a plus.
| 月薪 80,000元 ~ 140,000元 |
新竹市
新竹市東區公道五路三段1號7樓之8
| 1 |
[研發替代役] 數位晶片設計工程師(前端) / Digital IC Design Engineer (Frontend)
(理工科系職缺:是)
|
## Skill: - Familiar with Verilog RTL implementation from a matlab, python or c algiorithm. - Familiar with RTL simulation, timing analysis. - Familiar with FGPA digital validation and test pattern generation using (system)ILA, logic analyzer, high-speed oscilloscope, etc. - Familiar with Xilinx FPGA serdes IO, and selectIO. - Familiar with Xilinx IP design and packaging. - Familiar with at least one FPGA device. - Familiar with Custom IP and SoC integration is a plus.
|
## Job Description: The candidate will work closely with DSP algorithm team and software team to propose functional architecture and implement DSP algorithm using RTL and verified on a Xilinx FPGA. The verified design will either be passed to back-end for P&R or as a FPGA device product for early customer demo. The candidate will work with massive I/O throughputs using a parallel of high speed serdes.
| 月薪 70,000元 ~ 140,000元 |
新竹市
新竹市東區公道五路三段1號7樓之8
| 1 |
[研發替代役] 軟體工程師 / Software Engineer
(理工科系職缺:是)
|
- Understand algorithm, data structures, database, and other computer science fundamentals - Expert in at least one general programming language, such as: Python, C++, Java etc. - Open minded, fast learner, passionate about programming - (Optional) Familiar with Git - (Optional) Experience in SQL like MySQL, PostgreSQL etc - (Optional) Experience in docker - (Optional) Understand concept of CI/CD
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- Involved in core product development to be deployed in wide variety of devices, networking, and cloud service. - Architecture and algorithm/data structure design - API design, programming and testing - Protocol verification and design - Integrate 3rd party API and data source
| 新竹市東區公道五路三段1號7樓之8 |
新竹市
月薪 70,000元 ~ 140,000元
| 1 |
混合信號晶片設計工程師 (時脈電路) / Mixed-Signal IC Design Engineer (Clocking)
(理工科系職缺:是)
|
## Skill: - Familiar with cadence virtuoso schematic editor/ADE/MMSIM/layout flow. - Familiar with calibre DRC/LVS/PEX verification flow. - Has tapeout / measurement experience. - Has <=65nm TSMC process experience is a plus. - Candidate with ADPLL experience is a plus.
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Participate in phased-array transceiver SoC design ranging from L-band to W-band for state-of-the-art satellite communication or radar systems.
## Job Description: - Design PLL building blocks in CMOS process. - The building blocks assigned will be based on candidate's experiences and professional knowledge and corporate needs. - Possible building blocks of our interests include:
a.) Prescalar circuits. b.) Frequency Dividers c.) Frequency Multipliers d.) LO Drivers e.) Loop Filters. f.) Phase-frequency detectors
- PLL system simulation.
| 月薪 76,000元 ~ 160,000元 |
新竹市
新竹市東區公道五路三段1號7樓之8
| 1 |
混合信號晶片設計工程師(類比數位/數位類比轉換器) / Mixed-Signal IC Design Engineer (Data Converter)
(理工科系職缺:是)
|
## Skill: - Familiar with cadence virtuoso schematic editor/ADE/MMSIM/layout flow. - Familiar with calibre DRC/LVS/PEX verification flow. - Has tapeout / measurement experience. - Has <=65nm TSMC process experience is a plus. - High-speed SAR, pipelined, Sigma-Delta ADCs or Current Steering DACs tapeout experience is required.
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## Job Description: - ADC or DAC IC design. - ADC or DAC building blocks. - The building blocks assigned will be based on candidate's experiences and professional knowledge and corporate needs.
| 月薪 76,000元 ~ 160,000元 |
新竹市
新竹市東區公道五路三段1號7樓之8
| 1 |
[研發替代役] 射頻晶片設計工程師 / RFIC Design Engineer
(理工科系職缺:是)
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##Skill - Familiar with cadence virtuoso schematic editor/ADE/MMSIM/layout flow. - Familiar with calibre DRC/LVS/PEX verification flow. - Has tapeout / measurement experience. - Has <=65nm TSMC process experience is a plus.
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## Job Description: - Design transceiver building blocks in CMOS process. - The building blocks assigned will be based on candidate's experiences and professional knowledge and corporate needs. - Possible building blocks of our interests include: a.) Power Amplifers b.) Low Noise Amplifiers c.) RF Mixers d.) LO Drivers or RF signal drivers.
| 月薪 65,000元 ~ 130,000元 |
新竹市
新竹市東區公道五路三段1號7樓之8
| 1 |
[2021實習] EM模擬實習生
(理工科系職缺:是)
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- 熟悉ADS momentum / FEKO等電磁模擬軟體
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- 參與系統設計中的電磁模擬, 以傳輸線損耗與S參數模擬為主; - 完成電磁設計的對應文件
| 時薪 250元 ~ 300元 |
新竹市
新竹市東區公道五路三段1號7樓之8
| 1 |
[2021實習] 系統設計實習生
(理工科系職缺:是)
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- 具RF / Analog / Digital 電路設計相關背景
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- 協助系統工程師完成電路板系統設計及對應文件 - 參與系統工程師量測 - 參與元件資料庫建立及整理 - 其他主管交辦事項
| 日薪 2,400元 ~ 3,000元 |
新竹市
新竹市東區公道五路三段1號7樓之8
| 3 |
助理工程師 / Assistant Engineer
(理工科系職缺:是)
|
- 具RF / Analog / Digital 電路設計相關背景 - 熟悉Orcad / Allegro使用佳 - Microsoft Office
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- 協助系統工程師完成電路板系統設計及對應文件(儀器操作、新人教育訓練等) - 協助系統工程師量測 - 電子元件評估與選用 - 元件資料庫建立及整理 - 協助專案文件維護 - 完成主管交辦事項
| 月薪 32,000元 ~ 40,000元 |
新竹市
新竹市東區公道五路三段1號7樓之8
| 1 |
勞工安全 / 職業安全衛生管理員
(理工科系職缺:否)
|
- 熟知ISO45001運作 - 熟知ISO14001運作 - 熟知CNS45001、TOSHMS運作 - 具「職業安全衛生管理師證照」者或「甲級職業安全衛生業務主管」尤佳 - 具「防火管理人」證照者尤佳
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- 管理法規相關性評估、適用性評估、符合性評估之結果 - 識別潛在風險,降低或控制虛驚事件與事故發生 - 管理並督導自動檢查、檢點結果、定期檢查、重點檢查及作業環境測定結果 - 參與並協助主管執行年度營運相關的特殊的專案或計畫 - 協助其他ISO導入作業 - 其他主管指示或交辦事項
| 月薪 40,000元 ~ 50,000元 |
新竹市
新竹市東區公道五路三段1號7樓之8
| 1 |
MIS工程師 / MIS Engineer
(理工科系職缺:是)
|
- 熟悉Windows、Linux、VMware、網路、關聯式資料庫、Azure等IT架構 - 具備管理IT、資安軟體及硬體之經驗 - 具備基礎程式設計能力,如Python、Shell Script、HTML 、JavaScript 等 - 具有 Low-code Platform開發經驗。 - Open minded, fast learner, passionate about MIS/workflow optimization - (Optional) 熟悉MS Dataverse(Common data service) - (Optional) 熟悉Apex、Visualforce - (Optional) 熟悉LDAP
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- Salesforce CRM 管理與開發 (獨立或配合外部顧問) - D365 ERP/MS Office App管理與開發(獨立或配合外部顧問) - WindChill PLM 管理與開發(獨立或配合外部顧問) - 協助IT職務,如資安事件的防範與調查、伺服器管理與資料備份、使用者帳號的管理與建置、軟體授權、硬體設備規劃與維護、維護雲端等
| 月薪 76,000元以上 |
新竹市
新竹市東區公道五路三段1號7樓之8
| 1 |