公司人數:40
資本額:
地址:300 新竹市公道五路三段1號7F-8(A座)

洽詢電話:03-5750057 |

線上登錄履歷

創未來科技成立於2018年12月,為全球最薄全數位相控陣列雷達/通信系統整合開發領導廠商,自主研發所有關鍵專利技術,含括晶片、微封裝、雷達演算法、機械/散熱設計以及資訊系統設計等。本公司目前在超薄輕量化的相控陣列系統技術具有全球領導地位,產品持續於IEEE國際雷達會議、IEEE國際微波會議等知名國際會議或展覽大受矚目,在全球航太、新能源、國防產業等皆有合作客戶。

營業項目

1. 微型相控陣列雷達系統
2. 微型相控陣列通信系統
3. 巨量時空感測資料處理軟體系統

應徵須知

歡迎至104人力銀行了解更多職缺資訊或線上填寫資料

薪資福利

1. 彈性上下班。
2. 健全的升遷管道與頻繁的升遷機會。
3. 在職教育訓練。
4. 完善考核、專利獎勵制度
5. 績效獎金(視當年度營運及個人績效表現而定)。
6. Herman Miller Aeron人體工學座椅、電動升降工作桌。
7. 健身房會員補助(每年補助上限15K)。
8. 每年員工健康檢查。
9. 依法勞保/健保/勞退提繳。團體意外與醫療保險。
10. 三節獎金或禮品。
11. 婚喪喜慶補助、住院慰問金。
12. 不定期舉辦員工聚餐、活動補助。
13. 慶生禮金。
14. 生育禮金。
15. 年度旅遊。
16. 年終尾牙。



目前共有 8 個職缺類型

求才職稱資格條件工作內容待遇工作地點需求人數
數位晶片設計工程師(前端) / Digital IC Design Engineer (Frontend)

(理工科系職缺:)

## Skill:
- Familiar with Verilog RTL implementation from a matlab, python or c algiorithm.
- Familiar with RTL simulation, timing analysis.
- Familiar with FGPA digital validation and test pattern generation using (system)ILA, logic analyzer, high-speed oscilloscope, etc.
- Familiar with Xilinx FPGA serdes IO, and selectIO.
- Familiar with Xilinx IP design and packaging.
- Familiar with at least one FPGA device.
- Familiar with Custom IP and SoC integration is a plus.


## Job Description:
The candidate will work closely with DSP algorithm team and software team to propose functional architecture and implement DSP algorithm using RTL and verified on a Xilinx FPGA. The verified design will either be passed to back-end for P&R or as a FPGA device product for early customer demo. The candidate will work with massive I/O throughputs using a parallel of high speed serdes.
月薪 70,000元 ~ 140,000元 新竹市
新竹市東區公道五路三段1號7樓之8
3
C++軟體工程師 / C++ Software Engineer

(理工科系職缺:)

- experiences on software/hardware integration is a plus.
- experiences with SQL/NoSQL database is a plus.


- C++ object oriented programming
- protocol verification and design
月薪 70,000元 ~ 140,000元 新竹市
新竹市東區公道五路三段1號7樓之8
1
數位信號處理工程師 / DSP Engineer

(理工科系職缺:)

-(Optional) 應徵者若有熟悉下列信號處理之相關知識或技術之一項或多項者,敬請在求職履歷中特別註明並附相關經歷(曾參與的專題計畫或修習過的課程、或其他工作經驗等),將以更加優沃的待遇優先考慮:(強調此項者可以完全不熟悉FPGA實作)

- 矩陣分解(SVD, EVD, QR,等)
- 信號時頻分析及原理、
- 波束形成、
- 載波頻率偏移(CFO)之校正補償、
- Optimal receiver(例如MMSE接收器)
- compressive sensing演算法設計及原理
- 傳輸波形最佳化
- 子空間演算法(MUSIC, ESPRIT, 等)


1. Digital signal processing for wireless radar signals.
2. Performance evaluation of algorithm design.
3. (Optional) Some basic understanding of FPGA/RTL is a plus.
月薪 80,000元 ~ 140,000元 新竹市
新竹市東區公道五路三段1號7樓之8
1
[研發替代役] 數位晶片設計工程師(前端) / Digital IC Design Engineer (Frontend)

(理工科系職缺:)

## Skill:
- Familiar with Verilog RTL implementation from a matlab, python or c algiorithm.
- Familiar with RTL simulation, timing analysis.
- Familiar with FGPA digital validation and test pattern generation using (system)ILA, logic analyzer, high-speed oscilloscope, etc.
- Familiar with Xilinx FPGA serdes IO, and selectIO.
- Familiar with Xilinx IP design and packaging.
- Familiar with at least one FPGA device.
- Familiar with Custom IP and SoC integration is a plus.


## Job Description:
The candidate will work closely with DSP algorithm team and software team to propose functional architecture and implement DSP algorithm using RTL and verified on a Xilinx FPGA. The verified design will either be passed to back-end for P&R or as a FPGA device product for early customer demo. The candidate will work with massive I/O throughputs using a parallel of high speed serdes.
月薪 70,000元 ~ 140,000元 新竹市
新竹市東區公道五路三段1號7樓之8
1
[研發替代役] C++軟體工程師 / C++ Software Engineer

(理工科系職缺:)

- experiences on software/hardware integration is a plus.
- experiences with SQL/NoSQL database is a plus.


- C++ object oriented programming
- protocol verification and design
新竹市東區公道五路三段1號7樓之8 新竹市
月薪 70,000元 ~ 140,000元
1
混合信號晶片設計工程師 (時脈電路) / Mixed-Signal IC Design Engineer (Clocking)

(理工科系職缺:)

## Skill:
- Familiar with cadence virtuoso schematic editor/ADE/MMSIM/layout flow.
- Familiar with calibre DRC/LVS/PEX verification flow.
- Has tapeout / measurement experience.
- Has <=65nm TSMC process experience is a plus.
- Candidate with ADPLL experience is a plus.


Participate in phased-array transceiver SoC design ranging from L-band to W-band for state-of-the-art satellite communication or radar systems.

## Job Description:
- Design PLL building blocks in CMOS process.
- The building blocks assigned will be based on candidate's experiences and professional knowledge and corporate needs.
- Possible building blocks of our interests include:

a.) Prescalar circuits.
b.) Frequency Dividers
c.) Frequency Multipliers
d.) LO Drivers
e.) Loop Filters.
f.) Phase-frequency detectors

- PLL system simulation.
月薪 76,000元 ~ 160,000元 新竹市
新竹市東區公道五路三段1號7樓之8
1
混合信號晶片設計工程師(類比數位/數位類比轉換器) / Mixed-Signal IC Design Engineer (Data Converter)

(理工科系職缺:)

## Skill:
- Familiar with cadence virtuoso schematic editor/ADE/MMSIM/layout flow.
- Familiar with calibre DRC/LVS/PEX verification flow.
- Has tapeout / measurement experience.
- Has <=65nm TSMC process experience is a plus.
- High-speed SAR, pipelined, Sigma-Delta ADCs or Current Steering DACs tapeout experience is required.


## Job Description:
- ADC or DAC IC design.
- ADC or DAC building blocks.
- The building blocks assigned will be based on candidate's experiences and professional knowledge and corporate needs.
月薪 76,000元 ~ 160,000元 新竹市
新竹市東區公道五路三段1號7樓之8
1
[研發替代役] 射頻晶片設計工程師 / RFIC Design Engineer

(理工科系職缺:)

##Skill
- Familiar with cadence virtuoso schematic editor/ADE/MMSIM/layout flow.
- Familiar with calibre DRC/LVS/PEX verification flow.
- Has tapeout / measurement experience.
- Has <=65nm TSMC process experience is a plus.


## Job Description:
- Design transceiver building blocks in CMOS process.
- The building blocks assigned will be based on candidate's experiences and professional knowledge and corporate needs.
- Possible building blocks of our interests include:
a.) Power Amplifers
b.) Low Noise Amplifiers
c.) RF Mixers
d.) LO Drivers or RF signal drivers.
月薪 65,000元 ~ 130,000元 新竹市
新竹市東區公道五路三段1號7樓之8
1