| 求才職稱 | 資格條件 | 工作內容 | 待遇 | 工作地點 | 需求人數 |
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前端工程師
(理工科系職缺：是)
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## Job Description:
- Design and build GUI application on PC with Electron for 3D visualization (d3.js or three.js)
- Involve with product detail and schedule
## Skill:
- Familiar with front-end technology (HTML/CSS/JavaScript)
- Familiar with version control system (Git is preferred)
- Familiar with other JS frontend framework (Vue.js, ReactJS, Angular, etc.) is a plus
- Understand concept of CI/CD
- Self-motivated
- Able to work independently and remotely
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## Job Description:
- Design and build GUI application on PC with Electron for 3D visualization (d3.js or three.js)
- Involve with product detail and schedule
| 年薪 1000000-1200000 (12個月; 分紅獎金另計) |
新竹市
新竹市 或 遠端(一週進辦公室兩次)
| 1 |
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生管專員
(理工科系職缺：否)
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接受身份 上班族、應屆畢業生
工作經驗 不拘
學歷要求 大學、碩士
科系要求 商業及管理學科類,經濟社會及心理學科類,語文及人文學科類
語文條件 英文(聽:中等、說:中等、讀:中等、寫:中等)
其他條件 熟Excel資料分析。
有ERP系統經驗佳。
負責任、溝通能力佳、學習能力佳。
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1. 規劃及管控生產排程、交期，異常追蹤，協助與外部供應商聯繫。
2. 協助完成相關文件。
3. 撿料、進貨盤點、退料盤點、協助領料作業以及管理庫存異動。
4. 提出有關工作內容相關的修正建議。
5. 完成主管交辦業務
| 月薪 35,000元 ~ 55,000元 |
新竹市
新竹市
| 1 |
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FPGA設計工程師
(理工科系職缺：是)
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1. Familiar with Verilog RTL design.
2. Familiar with RTL simulation, timing analysis using Xilinx Vivado Design Suite.
3. Familiar with FGPA digital validation and test pattern generation using (system)ILA, logic analyzer, high-speed oscilloscope, etc.
4. Familiar with Xilinx FPGA serdes IO, and selectIO.
5. Familiar with Xilinx IP design and packaging.
6. Familiar with at least one Xilinx FPGA device.
7. Familiar with Xilinx HLS is a plus.
8. Familiar with Xilinx Zynq SoC is a plus.
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The candidate will work closely with DSP algorithm team and software team to propose functional architecture and implement DSP algorithm using Xilinx FPGA. The candidate will work with massive I/O throughputs using a parallel of high speed serdes.
| 月薪 70,000元 ~ 140,000元 |
新竹市
無需出差
| 1 |
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類比IC設計工程師
(理工科系職缺：是)
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1. Familiar with cadence virtuoso schematic editor/ADE/MMSIM/layout flow.
2. Familiar with calibre DRC/LVS/PEX verification flow.
3. Has tapeout / measurement experience.
4. Has <=65nm TSMC process experience is a plus.
5. Has 5G analog baseband IC design experience is a plus.
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Analog Filter and Variable Gain Filter IC design.
| 月薪 76,000元 ~ 160,000元 |
新竹市
新竹市東區公道五路三段1號7樓之8
| 1 |
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數位信號處理工程師 / DSP Engineer
(理工科系職缺：是)
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1. Digital signal processing for wireless radar signals.
2. Performance evaluation of algorithm design.
3. (Optional) Some basic understanding of FPGA/RTL is a plus.
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(Optional) 應徵者若有熟悉下列信號處理之相關知識或技術之一項或多項者，敬請在求職履歷中特別註明並附相關經歷(曾參與的專題計畫或修習過的課程、或其他工作經驗等)，將以更加優沃的待遇優先考慮：(強調此項者可以完全不熟悉FPGA實作)
- 矩陣分解(SVD, EVD, QR,等)
- 信號時頻分析及原理、
- 波束形成、
- 載波頻率偏移(CFO)之校正補償、
- Optimal receiver(例如MMSE接收器)
- compressive sensing演算法設計及原理
- 傳輸波形最佳化
- 子空間演算法(MUSIC, ESPRIT, 等)
| 月薪 70,000元以上 |
新竹市
新竹市東區公道五路三段1號7樓之8
| 1 |
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CMOS RF晶片設計工程師 / CMOS RFIC Design Engineer
(理工科系職缺：是)
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1. Familiar with cadence virtuoso schematic editor/ADE/MMSIM/layout flow.
2. Familiar with calibre DRC/LVS/PEX verification flow.
3. Has tapeout / measurement experience.
4. Has <=65nm TSMC process experience is a plus.
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CMOS RFIC circuit design for the transceiver building blocks, ex. PA/LNA/Mixer/LO and RF driver related circuit
| 月薪 76,000元 ~ 160,000元 |
新竹市
新竹市東區公道五路三段1號7樓之8
| 1 |