公司人數:300
資本額:2億
地址:新竹市力行一路一號一樓1C1

洽詢電話:03-6668828 | HR

線上登錄履歷

安霸(NASDAQ:AMBA),2004年成立於美國矽谷,並於同年10月成立於竹科,主要提供低功耗、超高畫質影音壓縮與影像處理半導體的解決方案。藉優越的技術與專利,安霸成為全球影像處理技術的領導商,並獲得GSA頒贈獎項,是全球IC 設計業中最受關注的企業。 我們將研發技術深耕台灣,開拓數位多媒體應用市場,除現有的產品應用,積極投入多元化消費性電子產品之數位多媒體核心處理器研發,更投入智慧型的視訊分析技術與人工智慧,為智慧型數位影音產品提供前瞻應用。

營業項目

隨著自動駕駛、人工智慧等新趨勢崛起,安霸亦積極從影像辨識推進到影像分析,將電腦視覺視為機器人、無人機、安全監控以及車用鏡頭市場的關鍵差異化技術。我們從世界各地網羅一流人才,組成先進智慧型的人工智慧與視訊分析技術團隊,並在系統單晶片中實現智慧型視訊與影像分析能力。智慧型的系統單晶片能增進視訊與影像資料在先進駕駛輔助系統(ADAS)、無人車自動駕駛、智慧型照相攝影機與空拍飛行器上的實用性,讓這些產品更貼近人心。

應徵須知

凡理工科碩、博班應屆畢業生,至安霸104校徵專區投遞履歷且參加說明會,就可拿到7-11禮卷喔!想了解更多校徵活動資訊、搶好康,請詳見安霸FB粉絲專頁!

▌104校徵專區:https://www.104.com.tw/job/6u7j0?jobsource=jolist_b_relevance
▌安霸FB粉專:https://zh-tw.facebook.com/ambarellatw/

※ 欲參加投履歷拿7-11禮卷活動,僅限在104校徵專區投履歷才符合活動資格喔!

薪資福利

◆ 制度類
1. 具市場競爭力之薪資水準
2. 加班免費供應晚餐
3. 人性化管理,彈性工作時間
4. 員工旅遊
5. 年度調薪
6. 目標達成獎金
7. 享股票選擇權機會

◆ 請/休假制度
1. 週休二日
2. 女性同仁生理假
3. 優於勞基法之特休假
4. 育嬰假
5. 陪產假
6. 全薪病假
7. 家庭照顧假

◆ 補助類
1. 婚喪喜慶補助
2. 生育津貼
3. 育兒補助
4. 社團補助
5. 二節禮金
◆ 其他
1. 免費健康檢查
2. 特約商店

◆ 保險類
1. 勞/健/團保
2. 眷屬團保(依員工費率自費加保)



目前共有 5 個職缺類型

求才職稱資格條件工作內容待遇工作地點需求人數
Application Engineer

(理工科系職缺:)

學歷要求:碩士以上
科系要求:電機電子工程相關、資訊工程相關
語文條件:英文 -- 聽 /中等、說 /中等、讀 /中等、寫 /中等
擅長工具:C、C++
工作技能:不拘
其他條件:
* Strong C programming debugging skills
* Familiar with Embedded RTOS System Programming


* APP development on embedded system
* Customer project debug and support
* Business travel needed
面議 新竹市
新竹市科學工業園區力行一路1號1樓C1
5
Computer Vision Engineer

(理工科系職缺:)

工作經歷:不拘,歡迎社會新鮮人
學歷要求:碩士以上
科系要求:資訊工程相關、電機電子工程相關
語文條件:英文 -- 聽 /中等、說 /中等、讀 /中等、寫 /中等
擅長工具: C、C++
工作技能:不拘
其他條件:
*Strong background of image processing /computer vision.
*Knowledge of C/C++ performance fine tune will be a plus.
*Familiar with embedded system programming will be a plus.
*Familiar with multimedia standards (JPEG,MPEG 1/2/4, H.264, VC-1) will be a plus.


The job is to design/verify/improve the algorithm for computer vision running on embedded system. 面議 新竹市
新竹市科學園區安霸股份有限公司
5
CV Application and Toolchain Engineer

(理工科系職缺:)

工作經歷:不拘,歡迎社會新鮮人
學歷要求:碩士以上
科系要求:資訊工程相關、電機電子工程相關
語文條件:英文 -- 聽 /中等、說 /中等、讀 /中等、寫 /中等
擅長工具:C、C++
工作技能:不拘
其他條件:
*Skilled in C/C++ (and/or) Python is required
*Strong background of CNN-based computer vision knowledge
*Familiar with computer vision and machine learning framework like Caffe/Caffe2, Tensorflow, Pytorch
*Familiar with computer architecture and parallel computing concept is a plus
*Experience on compiler design is a plus


* Develop the computer vision toolchain to ensure the efficient use of hardware resources
* Develop the computer vision application on top of Ambarella computer vision chips
面議 新竹市
新竹市科學園區安霸股份有限公司
5
VLSI Design Verification Engineer

(理工科系職缺:)

工作經歷:不拘,歡迎社會新鮮人
學歷要求:碩士以上
科系要求:不拘
語文條件:英文 -- 聽 /中等、說 /中等、讀 /中等、寫 /中等
擅長工具:SystemVerilog 、Python or Perl
工作技能:不拘
其他條件:
* Minimum Master degree majoring in EE/CE/CS related fields
* Prefer who has 2+ years of hands-on experiences on VLSI design verification
* Experiences of transaction-based verification at higher-level of abstractions (e.g. UVM) is a big plus.


At Ambarella, we gather brilliant minds together to push computer vision technology forward. We're seeking a VLSI design verification (DV) engineer who will verify our most cutting-edge SOCs and components inside SOC.

A DV engineer works with designers to make sure design meets specification. Firstly, a DV engineer creates a test plan. A test plan plots in details on what tests you need/want to create and how you can apply the tests to the design under verification (DUV).

Secondly, a DV engineer writes a test bench which drives stimulus (a test) to DUV and writes monitor(s) and checker(s) to validate the DUV's outputs.

Thirdly, to fully verify a DUV, a DV engineer runs hundreds, thousands, or even millions of tests depending on the complexity of DUV - we call it regression. A DV engineer then works with designer(s) to clean up all the failures in the regression.

Lastly and most importantly, a DV engineer must work with designers to review coverage data - it tells us whether all Verilog statements within DUV is truly and fully exercised or not so that we can guarantee the verification quality and deliver high quality designs.
面議 新竹市
新竹市科學園區安霸股份有限公司
5
Physical Designer

(理工科系職缺:)

工作經歷:不拘,歡迎社會新鮮人
學歷要求:碩士以上
科系要求:電機電子工程相關、資訊工程相關、光電工程相關
語文條件:英文 -- 聽 /中等、說 /中等、讀 /中等、寫 /中等
擅長工具:Perl、TCL、ASIC、EDA、Verilog
工作技能:不拘
其他條件:
* Minimum Master degree majoring in EE/CE/CS related fields.
* Good knowledge in CMOS digital circuit design.
* Skill sets of one of Cadence/Synopsys/Mentor EDA tools is a plus.
* Concept on executing floorplanning, P&R timing closure and physical verification.
* Enthusiastic in developing design flow methodology and problem solving skill.
* Familiar with Perl/TCL scripting is a plus.
* Proficiency in speaking and writing English is a plus.
* Good communication skill, team spirit, initiative, innovative and fast learning.


* Executing floorplanning, design closures on timing, signal integrity, power integrity, DFM as well as physical verification.
* Tapeout with multi-million gates count SOC design on leading edge technologies.
* Develop physical design flows/solutions on the latest cutting edge technology node.
面議 新竹市
新竹市科學園區安霸股份有限公司
5