公司人數:300
資本額:2億
地址:新竹市力行一路一號一樓1C1

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安霸(NASDAQ:AMBA),2004年成立於美國矽谷,並於同年10月成立於竹科,主要提供低功耗、超高畫質影音壓縮與影像處理半導體的解決方案。藉優越的技術與專利,安霸成為全球影像處理技術的領導商,並獲得GSA頒贈獎項,是全球IC 設計業中最受關注的企業。 我們將研發技術深耕台灣,開拓數位多媒體應用市場,除現有的產品應用,積極投入多元化消費性電子產品之數位多媒體核心處理器研發,更投入智慧型的視訊分析技術與人工智慧,為智慧型數位影音產品提供前瞻應用。

營業項目

隨著自動駕駛、人工智慧等新趨勢崛起,安霸亦積極從影像辨識推進到影像分析,將電腦視覺視為機器人、無人機、安全監控以及車用鏡頭市場的關鍵差異化技術。我們從世界各地網羅一流人才,組成先進智慧型的人工智慧與視訊分析技術團隊,並在系統單晶片中實現智慧型視訊與影像分析能力。智慧型的系統單晶片能增進視訊與影像資料在先進駕駛輔助系統(ADAS)、無人車自動駕駛、智慧型照相攝影機與空拍飛行器上的實用性,讓這些產品更貼近人心。

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目前共有 5 個職缺類型

求才職稱資格條件工作內容待遇工作地點需求人數
Computer vision engineer
工作經歷:不拘,歡迎社會新鮮人
學歷要求:碩士以上
科系要求:資訊工程相關、電機電子工程相關
語文條件:英文 -- 聽 /中等、說 /中等、讀 /中等、寫 /中等
擅長工具:不拘
工作技能:不拘
其他條件:
*Strong background of image processing /computer vision.
*Knowledge of C/C++ performance fine tune will be a plus.
*Familiar with embedded system programming will be a plus.
*Familiar with multimedia standards (JPEG,MPEG 1/2/4, H.264, VC-1) will be a plus.


The job is to design/verify/improve the algorithm for computer vision running on embedded system. 面議 新竹市
新竹市科學園區安霸股份有限公司
5
CV Application and Toolchain Engineer
工作經歷:不拘,歡迎社會新鮮人
學歷要求:碩士以上
科系要求:資訊工程相關、電機電子工程相關
語文條件:英文 -- 聽 /中等、說 /中等、讀 /中等、寫 /中等
擅長工具:不拘
工作技能:不拘
其他條件:
*Skilled in C/C++ (and/or) Python is required
*Strong background of CNN-based computer vision knowledge
*Familiar with computer vision and machine learning framework like Caffe/Caffe2, Tensorflow, Pytorch
*Familiar with computure architecture and parallel computing concept is a plus
*Experience on compiler design is a plus


Develop the computer vision toolchain to ensure the efficient use of hardware resources
Develop the computer vision application on top of Ambarella computer vision chips
面議 新竹市
新竹市科學園區安霸股份有限公司
5
Physical Designer
工作經歷:不拘,歡迎社會新鮮人
學歷要求:碩士以上
科系要求:不拘
語文條件:英文 -- 聽 /精通、說 /精通、讀 /精通、寫 /精通
擅長工具:Shell、UNIX、C、C++、Perl、EDA
工作技能:不拘
其他條件:
* Minimum Master degree majoring in EE/CE/CS related fields
*7~10 years of working experience.
* Experiences in tapeout with multi-million gates count SOC designs using 65nm and 40nm technologies, 32nm/28nm design experience is a plus.
* Solid skill sets of one of Cadence/Synopsys/Magama/Mentor EDA APR tools.
*Familiar with the design methodology on UDSM timing/power/DFM closures and low power designs
* Familiar with Unix shell, Perl/TCL scripting and C/C++ programming.
* Be capable of implementing/enhancing design infrastruture dynamically to constantly improve the design productivity efficiency.
* Have capabilities for demonstrating high creativity in project planning and execution.
* Have good communicative and interpersonal skills, personality of patience and carefulness, initiative and innovation, and acute sensitivity in the change of advanced technology.
* Proficiency in speaking and writing English.


1. Tapeout with multi-million gates count SOC design on cutting-edge technologies.
2. Develop UDSM design methodology for timing/power/reliability/DFM closures and low power designs.
3. Implement and enhance design infrastructure for the increases on productivity and quality.
面議 新竹市
新竹市科學園區安霸股份有限公司
5
Verification Engineer
工作經歷:不拘,歡迎社會新鮮人
學歷要求:碩士以上
科系要求:電機電子工程相關、資訊工程相關、光電工程相關
語文條件:英文 -- 聽 /中等、說 /中等、讀 /中等、寫 /中等
擅長工具:C、C++、Perl、TCL
工作技能:不拘
其他條件:
*Desired 2+ years of hands-on experiences in SoC design verification.
*Experiences with OVM/UVM/VMM and familiarity with transaction-based verification at higher-level of abstractions is a big plus.
*Be familiar with SystemVerilog
*Be familiar with C/C++


1. Develop Test benches for DSP logic blocks, processor cores, coprocessor cores and other digital logic devices in System Verilog, C and C++.
2. Write measurable verification plans for the above mentioned DUT-s for pre-silicon chip validation at block or full chip level.
3. Write and debug tests for the above-mentioned DUT-s using SystemVerilog, Perl, Assembly, C, C++ and possibly other languages.
4. Write reusable constraint random test generators with automated checking.
5. Write coverage monitors to evaluate the coverage of the DUT-s.
6. Apply static or dynamic assertion based verification where it has best ROI.
7. Create sub-system and system level tests pre-and-post silicon.
面議 新竹市
新竹市科學園區安霸股份有限公司
5
2019 Ambarella Intern (Summer)
MS students major in EE, CE and CS related fields.

The intern students will gain and develop IC design skills and knowledge in the cutting edge 7nm through daily R&D interactions and job assignments for our product developments.

The topics for the IC design intern jobs including, but not limited to,
1. Fault simulation and analyses for ADAS safety function requirements
2. Design methodology of power integrity in 7nm IC design
3. Interconnection routing efficiency in IC design using 7nm EUV lithography process
4. Aging effect impact in performance and reliability of auto grade product and its methodology in modeling and alleviation.
面議 新竹市
新竹科學園區安霸股份有限公司
5